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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 3 1 publication order number: ncn6004a/d ncn6004a dual sam/sim interface integrated circuit the ncn6004a is an interface ic dedicated for secured access module reader/writer applications. it allows the management of two external iso/emv cards thanks to a simple and flexible microcontroller interface. several ncn6004a interfaces can share a single data bus, assuming the external mpu provides the right chip select signals to identify each ic connected on the bus. a built in accurate protection system guarantees timely and controlled shutdown in the case of external error conditions. on top of that, the ncn6004a can independently handle the power supply, in the range 2.7 v to 5.0 v input voltage, provided to each external smart card. the interface monitors the current flowing into each smart card, a flag being set in the case of overload. features ? separated, built?in dc/dc converters supply v cc power to external cards ? 100% compatible with iso 7816?3, emv and gie?cb standards ? fully gsm compliant ? individually programmable iso/emv clock generator ? built?in programmable crd_clk stop function handles run or high/low state ? programmable crd_clk slopes to cope with wide operating frequency range ? programmable independent v cc supply for each smart card ? support up to 65 ma v cc supply to each iso/emv card ? multiple ncn6004a parallel operation on a shared bus ? 8 kv/human model esd protection on each interface pin ? provides c4/c8 channels ? provides 1.8 v, 3.0 v or 5.0 v card supply voltages ? pb?free package is available* typical applications ? set top box decoder ? atm multi systems, pos, handheld terminals ? internet e?commerce pc interface ? multiple self serve automatic machines ? wireless phone payment interface ? automotive operating time controller *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagram device package shipping ? ordering information ncn6004aftbr2 tqfp48 2000/tape & ree l tqfp48 case 932f plastic 1 48 ncn6004aftbr2g tqfp48 (pb?free) 2000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. 1 a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package ncn6004a awlyywwg
ncn6004a http://onsemi.com 2 crd_io_a crd_rst_a crd_clk_a crd_vcc_a crd_c4_a crd_c8_a crd_det_a crd_io_b crd_rst_ b crd_clk_b crd_vcc_b crd_c8_b crd_c4_b crd_det_ b pwr_on status a0 a1 reset_a i/o_a clock_in_a c4_a c8_a pwr_vcc_a pwr_gnd l1b l2b l2a l1a anlg_gnd a2 anlg_vcc pwr_vcc_b a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 card_sel en_rpu i/o_b reset_b clock_in_b c4_b c8_b 45 46 47 48 anlg_gnd pwr_gnd anlg_gnd mux_mod e pgm cs int figure 1. pin diagram 8 7 6 5 8 7 6 5 gnd gnd data port#a data port#b mpu bus micro controller 7 pwr_on 8 status a0 1 a1 2 card_sel 5 6 i/o_a 9 reset_a 10 c4_a 11 c8_a 12 clk_in_a 13 a2 3 a3 4 en_rpu mux_mode 47 anlg_gnd 14 anlg_gnd 48 anlg_vcc 42 anlg_gnd 43 clk_in_b 15 c8_b 16 c4_b 17 reset_b 18 i/o_b 19 c3 10 f c1 10 f v cc v cc det 17 1 rst 2 clk 3 c4 4 c8 i/o vpp gnd det 18 j1 smartcard # a det 17 1 2 3 4 det 18 j2 smartcard # b gnd gnd gn d gnd pwr_vcc_a 28 pwr_gnd 36 crd_det_a 20 crd_vcc_a 29 crd_clk_a 30 crd_io_a 24 crd_det_b 41 crd_vcc_b 32 crd_clk_b 31 crd_io_b 37 crd_rst_a 23 crd_rst_b 38 crd_c4_a 22 crd_c8_a 21 crd_c4_b 39 crd_c8_b 40 pwr_vcc_b 33 pwr_gnd 25 gn d v cc v cc pgm cs int 100 nf l1 l1a l2a l2b l1b figure 2. typical application v cc rst clk c4 c8 i/o vpp gnd c4 22 h l2 22 h 35 34 26 27 46 44 45 chip select irq c2 10 f gnd ncn6004a
ncn6004a http://onsemi.com 3 35 36 31 30 20 41 24 37 23 38 29 34 25 l1b l2b 32 card#a detection card#b detection i/o#a i/o#b clk#a clk#b clk#a clk#b det#b gnd 21 40 39 22 crd_c4a crd_c8a crd_c8b crd_c4b crd_ioa crd_iob crd_clka pwr_gnd pwr_gnd crd_vcca crd_vccb crd_clkb crd_rsta crd_rstb 33 28 c4a c8a c4b c8b pwr_vcca pwr_vccb crd_detb crd_deta reset_a clk_a clk_b gnd figure 3. block diagram 13 7 47 8 1 15 100 k input voltage 42 6 anlg_vcc pwr_on a0 a1 clk_ina clk_inb agnd 43 a2 a3 2 3 5 card_sel gnd int cs pgm monitor v cc v cc io_a rst_a c4a c8a io_b rst_b c4b c8b cntl cntl 4 27 9 10 26 50 k 16 dc/dc converter card #a dc/dc converter pins drivers pins drivers card#a card#b card#b card#a sequencer card#b sequencer interrupt block clock#a clock#b digital block det#b det#a 17 12 45 11 i/o_a i/o_b c4a c8a 18 19 c4b c8b reset_a en_rpu mux_mode 44 26 k 100 k reset_b divider divider io_a c4a c8a io_b c4b c8b control analog & digital multiplex 100 k 100 k 26 k 100 k 100 k 100 k rst_a rst_b note: an internal active pull down device forces all the smart card pins to zero when the chip is deactivated. det#a reset_a l1a l2a 46 status v cc 50 k
ncn6004a http://onsemi.com 4 pin description pin symbol type description 1 a0 input this pin is combined with cs , a1, a2, a3, card_sel and pgm to program the chip mode of operation, the crd_vcc voltage value, and to read the data provided by the internal status register (table 1). 2 a1 input this pin is combined with cs , a0, a2, a3, card_sel and pgm to program the chip mode of operation, the crd_vcc voltage value, and to read the data provided by the internal status register (table 1). 3 a2 input this pin is combined with cs , a0, a1, a3, card_sel and pgm to program the chip mode of operation, the crd_vcc voltage value, and to read the data provided by the internal status register (table 1). 4 a3 input this pin is combined with cs , a0, a1, a2, card_sel and pgm to program the chip mode of operation, the crd_vcc voltage value, and to read the data provided by the internal status register (table 1). 5 card_sel input this pin provides logic identification of the card #a/card #b external smart card. the logic signal is set up by the external microcontroller. card_sel = high selection of the smart card a connected to pins 20, 21, 22, 23, 24, 29 and 30 (respectively crd_det_a, crd_c8_a, crd_c4_a, crd_rst_a, crd_io_a, crd_vcc_a and crd_clk_a). card_sel = low selection of the smart card b connected to pins 41, 39, 40, 31, 38, 37, and 32 (respectively crd_det_b, crd_c4_b, crd_c8_b, crd_clk_b, crd_rst_b, crd_io_b, and crd_vcc_b). 6 pgm digital input this pin is combined with cs , a0, a1, a2, a3, and card_sel to program the chip mode of operation and to read the data provided by the internal status register (figure 4 and table 1). pgm = h the ncn6004a is under normal operation and all the data with the external card can be exchanged using any of the smart card a or smart card b lines pgm = low the ncn6004a runs the programming mode and related parameters can be re programmed according to a given need. in this case, the related card side logic signals are latched in their previous states and no transaction can occurs. the programmed states are latched upon the pgm rising slope (figure 4). 7 cs digital input this pin provides the chip select function for the ncn6004a device. cs = high pins a0, a1, a2, a3, card_sel, pgm , pwr_on, reset_a, reset_b, c4_a, c4_b, c8_a, c8_b, i/o_a and i/o_b are disabled, the pre activated crd_vcc maintains it?s currently programmed value. cs = low pins a0, a1, a2, a3, card_sel, pgm , pwr_on, reset_a, reset_b, c4_a, c4_b, c8_a, c8_b, i/o_a and i/o_b are activated, all the functions being available.an internal pull up resistor, connected to v cc , provides a logic bias when the external p is in the high impedance state. 8 pwr_on digital input this pin activates or deactivates the dc/dc converter selected by card_sel upon positive/negative going transient. pwr_on = positive going high dc/dc activated pwr_on = negative going l dc/dc switched off, no power is applied to the associated output crd_vcc pin. since uncontrolled action could take place during the rise voltage of the related crd_vcc_x output, care must be observed to avoid a pwr_on negative going transient during this period of time. to avoid any logical latch up, using a minimum 1.0 ms delay is recommended prior to power down the related dc/dc converter following a power up command (figure 12). 9 i/o_a input/output this pin carries the data transmission between an external microcontroller and the external smart card #a. a built?in bi?directional level translator adapts the signal flowing between the card and the mcu. the level translator is enabled when cs = low. since a dedicated line is used to communicate the data between the mpu and the smart card, the user can activate the two channels simultaneously, assuming the p provides a pair of i/o lines. when mux_mode = high, this pin provides an access to either card a or b i/o by means of card_sel selection bit. on the other hand, the internal pull up resistor is automatically disconnected when mux_mode = high, avoiding a current overload on the i/o line, regardless of the en_rpu logic level. this pull up resistor is under the en_rpu control when mux_mode = low.
ncn6004a http://onsemi.com 5 pin description (continued) pin description type symbol 10 reset_a input the signal present on this pin is translated to the rst pin of the external smart card #a. the cs signal must be low to vali date the reset f unction, regardless of the selected card. assuming the p provides two independent lines to control the reset pins, the ncn6004a can control two cards simultaneously. when mux_mode = high, this pin provides an access to either card a or b reset by means of card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 11 c4_a input this pin controls the card #a c4 contact th e signal can be either de?multiplexed, at mpu level, or is multiplexed with c4_b, depending upon the mux_mode logic state. when mux_mode = high, this pin provides an access to either card a or b c4 channel by means of card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 12 c8_a input this pin controls the card #a c8 contact. th e signal can be either de?multiplexed, at mpu level, or is multiplexed with c8_b, depending upon the mux_mode logic state. when mux_mode = high, this pin provides an access to either card a or b c8 channel by means of card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 13 clock_in_a clock input, high impedance the signal present on this pin comes from either the mcu master clock, or from any signal fulfilling the logic level and frequency specifications. this signal is fed to the internal clock selection circuit prior to be connected to the external smart card #a. each of the external card can have different division ratio, depending upon the state of the crd_sel pin and associated programming bits. the built?in circuit can be programmed to 1/1, 1/2, 1/4 or 1/8 frequency division ratio. this input is valid and routed to either crd_clk_a _divider or crd_clk_b_divider regardless of the mux_mode state, depending upon the clk_d_a/crd_d_b and card_sel programmed states (table 1). although this input supports the signal coming from a crystal oscillator, care must be observed to avoid digital levels outside the specified v ih /v il range. similarly, the input clock signal shall have rise and fall times compatible with the operating frequency. 14 anlg_gnd power this pin is the ground reference for both analog and digital signals and must be connected to the system ground. care must be observed to provide a copper pcb layout designed to avoid small signals and power transients sharing the same track. good high frequency techniques are strongly recommended. 15 clock_in_b clock input, high impedance the signal present on this pin comes from either the mcu master clock, or from any signal fulfilling the logic level and frequency specifications. this signal is fed to the internal clock selection circuit prior to be connected to the external smart card #b. each of the external card can have different division ratio, depending upon the state of the crd_sel pin and associated programming bits. the built?in circuit can be programmed to 1/1, 1/2, 1/4, or 1/8 frequency division ratio. this input is valid and routed to either crd_clk_b_divider or crd_clk_a_divider regardless of the mux_mode state, depending upon the crd_d_b/crd_d_a and card_sel programmed states (table 1). although this input supports the signal coming from a crystal oscillator, care must be observed to avoid digital levels outside the specified v ih /v il range. similarly, the input clock signal shall have rise and fall times compatible with the operating frequency. 16 c8_b input this pin controls the card #b c8 contact. the signal can be either de ?multiplexed, at mpu level, or is multiplexed with c8_a, depending upon the mux_mode logic state. when mux_mode = high, this pin is internally disable, a pull up resistor is connected to v cc (regardless of the logic state of en_rpu is), and the access to card b takes place by c8_a associated with card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 17 c4_b input this pin controls the card #b c4 contact. the signal can be either de ?multiplexed, at mpu level, or is multiplexed with c8_a, depending upon the mux_mode logic state. when mux_mode = high, this pin is internally disable, a pull up resistor is connected to v cc , (regardless of the logic state of en_rpu), and the access to card b takes place by c4_a associated with card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low.
ncn6004a http://onsemi.com 6 pin description (continued) pin description type symbol 18 reset_b input the signal present on this pin is translated to the rst pin of the external smart card #b. the cs signal must be low to valid the reset function, regardless of the selected card. assuming the p provides two independent lines to control the reset pins, and mux_mode = low, the ncn6004a can control two cards simultaneously. when mux_mode = high, this pin is internally disable, a pull up resistor is connected to v cc , (regardless of the logic state of en_rpu), and the access to card b takes place by reset_a associated with card_sel selection bit. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 19 i/o_b input/output this pin carries the data transmission between an external microcontroller and the external smart card #b. a built?in bi?directional level translator adapts the signal flowing between the card and the mcu. the level translator is enabled when cs = low. the signal present on this pin is latched when cs = high. since a dedicated line is used to communicate the data between the p and the smart card, (assuming mux_mode = low) the user can activate the two channels simultaneously, assuming the p provides a pair of i/o lines. when mux_mode = high, this pin is internally disable, the pull up resistor is connected to v cc , (regardless of the logic state of en_rpu), and the access to card b takes place by i/o_a associated with card_sel selection bit. 20 crd_det_a input this pin senses the signal coming from the external smart card connector to detect the presence of card #a. the polarity of the signal is programmable as normally open or normally close switch. the logic signal will be activated when the level is either low or high, with respect to the polarity defined previously. by default, the input is normally open. a built?in circuit prevents uncontrolled short pulses to generate an int signal. the digital filter eliminates pulse width below 50 s (see spec). 21 crd_c8_a output this pin controls the card #a c8 contact, according to the iso7816 specifications. a built?in level shifter is used to adapt the card and the c, regardless of the power supply voltage of each signals. the signal present at this pin is latched upon either card_sel =l, or cs = h or pgm = l, and resume to a transparent mode when card #a is selected and operates in the transfer mode.the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_a startup time. 22 crd_c4_a output this pin controls the card #a c4 contact, according to the iso7816 specifications. a built?in level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. the signal present at this pin is latched upon either card_sel = l, or cs = h, or pgm = l, and resume to a transparent mode when card #a is selected and operates in the transfer mode. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_a startup time. 23 crd_rst_a output this pin is connected to the external smart card #a to support the reset signal. a built?in level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. the signal present at this pin is latched upon either card_sel = low, or when cs or pgm returns to a high, and resume to a transparent mode when card #a is selected. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_a startup time. 24 crd_io_a input/output this pin carries the data serial connection between the external smart card #a and the microcontroller. a built?in bidirectional level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. this pin is biased by a pull up resistor connected to crd_vcc_a. when cs = high, the crd_io_a holds the previous i/o logic state and resume to a normal operation when this pin is reactivated. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_a start?up time. 25 pwr_gnd power this pin carries the power current flow coming from the built in dc/dc converters. it is associated with the external card # a. it must be connected to the system ground and care must be observed at pcb layout level to avoid the risk of spike voltages on the logic lines. 26 l2_a power connects one side of the external dc/dc converter inductor #a (note 1). 27 l1_a power connects one side of the external dc/dc converter inductor #a (note 1). 1. the external inductors shall preferably have the same values. depending upon the power absorbed by the load, the inductor can range from 10 h to 47 h. to achieve the highest yield, the inductor shall have an esr < 1.0 .
ncn6004a http://onsemi.com 7 pin description (continued) pin description type symbol 28 pwr_vcc_a power this pin is connected to the positive external power supply. the device sustains any voltage from +2.7 v to +5.5 v. this voltage supplies the ncn6004a internal circuits and is regulated by the internal dc/dc converter to provide the dc voltage to the external card. a high quality capacitor must be connected across pin 28 and pwr_gnd, 10 f/6.0 v ceramic x7r or x5r type is recommended. note: the voltage present at pin 28 and 33 must be equal to the voltage present at pin 42. 29 crd_vcc_a power this pin provides the power supply to the external smart card #a. the v cc voltage is defined by programming the ncn6004a accordingly. since the cards have independent dc/dc converter, the output voltage can have any value independently from card_b. a high quality, low esr capacitor is mandatory to achieve the v cc specifications. using two 4.7 f/6.0 v ceramic x7r or x5r capacitors in parallel is recommended. 30 crd_clk_a output this pin is connected to the clk external smart card #a pin. the signal comes from the built?in frequency divider dedicated to the #a card. the clock is selected and controlled by setting the logic inputs according to table 1. the slope of the output clock can be selected between one of the two programmable mode: slow or fast (table 8). the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_a startup time. 31 crd_clk_b output this pin is connected to the clk external smart card #b pin. the signal comes from the built?in frequency divider dedicated to the #b card. the clock is selected and controlled by setting the logic inputs according to table 1. the slope of the output clock can be selected between one of the two programmable mode: slow or fast (table 8). the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_b startup time. 32 crd_vcc_b power this pin provides the power supply to the external smart card #b. the v cc voltage is defined by programming the ncn6004a accordingly. since the cards have independent dc/dc converter, the output voltage can have any value independently from card_a. a high quality, low esr capacitor is mandatory to achieve the v cc specifications. using two 4.7 f/6.0 v ceramic x7r or x5r capacitors in parallel is recommended. 33 pwr_vcc_b power this pin is connected to the positive external power supply. the device sustains any voltage from +2.7 v to +6.0 v. this voltage supplies the ncn6004a internal circuits and is regulated by the internal dc/dc converter to provide the dc voltage to the external card. a high quality capacitor must be connected across pin 33 and pwr_gnd, 10 f/6.0 v ceramic x7r type is recommended. note: the voltage present on pin 28 and 33 must be equal to the voltage present on pin 42 34 l2b power connects one side of the external dc/dc converter inductor #b (note 1). 35 l1b power connects one side of the external dc/dc converter inductor #b (note 1). 36 pwr_gnd power this pin carries the power current flow coming from the built in dc/dc converters. it is associated with the external card # b. it must be connected to the system ground and care must be observed at pcb layout level to avoid the risk of spike voltages on the logic lines. 37 crd_io_b input/output this pin carries the data serial connection between the external smart card #b and the microcontroller. a built?in bi?directional level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. this pin is biased by a pull up resistor connected to crd_vcc_a. when cs = high, the crd_io_a holds the previous i/o logic state and resume to a normal operation when this pin is reactivated. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_b startup time. 38 crd_rst_b output this pin is connected to the external smart card #b to support the reset signal. a built?in level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. the signal present at this pin is latched upon either card_sel or cs or pgm positive going transient and resume to a transparent mode when card #b is selected. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_b startup time. 1. the external inductors shall preferably have the same values. depending upon the power absorbed by the load, the inductor can range from 10 h to 47 h. to achieve the highest yield, the inductor shall have an esr < 1.0 .
ncn6004a http://onsemi.com 8 pin description (continued) pin description type symbol 39 crd_c4_b output this pin controls the card #b c4 contact, according to the iso specification. a built?in level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. the signal present at this pi n is latched upon either card_sel or cs or pgm positive going transient and resume to a transparent mode when card #b is selected. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_b startup time. 40 crd_c8_b output this pin controls the card #b c8 contact, according to the iso specification. a built?in level shifter is used to adapt the card and the mcu, regardless of the power supply voltage of each signals. the signal present at this pin is latched upon either card_sel or cs or pgm positive going transient and resume to a transparent mode when card #b is selected. the pin is hardwired to zero, the bias being provided by the v cc supply, when either the v cc voltage drops below 2.7 v, or during the crd_vcc_b startup time. 41 crd_det_b input this pin senses the signal coming from the external smart card connector to detect the presence of card #b. the polarity of the signal is programmable as normally open or normally close switch. the logic signal will be activated when the level is either low or high, with respect to the polarity defined previously. by default, the input is normally open. a built?in circuit prevents uncontrolled short pulses to generate an int signal. the digital filter eliminates pulse width below 50 s. 42 anlg_vcc power this pin is connected to the positive external power supply. the device sustains any voltage from +2.7 v to +5.5 v. this voltage supplies the ncn6004a internal analog and logic circuits. a high quality capacitor must be connected across this pin and anlg_gnd, 10 f/6 v is recommended. a set of extra pins (28 and 33) are provided to connect the power supply to the internal dc/dc converter. note: the voltage present at pin 28 and 33 must be equal to the voltage present at pin 42 43 anlg_gnd ground this pin is the ground reference for both analog and digital signals and must be connected to the system ground. care must be observed to provide a copper pcb layout designed to avoid small signals and power transients sharing the same track. good high frequency techniques are strongly recommended. 44 mux_mode input this pin selects the mode of operation of the card signals from the mpu side. when mux_mode = low, all the card signals are fully de?multiplexed and data transfers can take place with both cards simultaneously. on top of that, both cards can be accessed during the programming sequence, assuming the external microcontroller is capable to run multi tasks software. when mux_mode = high, all the card signals are multiplexed and the communications with the cards shall take place in a sequential mode. the card is selected by setting card_sel high or low. the internal logic will disable the card_b inputs and use card_sel inputs as a single channel to controls both output smart cards sequentially when mux_mode = h. moreover, when mux_mode = high, all the b channel p dedicated pins, except clock_in_b, pin 15, are forced to a high level by means of internal pull up resistors. it is not necessary to connect these pins (16, 17, 18 and 19) to an external bias voltage, but it is mandatory to avoid any connections to ground. on the other hand, in this case the internal pull up resistor connected across i/o_a, pin 9 and v cc is automatically disconnected to avoid a current overload on the i/o line. 45 en_rpu input this pin provides a logic input to valid or not the internal pullup resistors connected across each i/o, reset, c4 and c8 lines and anlg_vcc. when en_rpu = high, the pull up resistors are connected when en_rpu = low, the pull up resistors are disconnected and it is up to the designer to set up the external resistor to cope with the iso/emv specifications. the logic signal must be set up prior to apply the anlg_vcc supply. once the logic mode has been acknowledged by the internal power on reset, it cannot be changed until a new startup sequence is launched. 46 status output this pin provides a logic state related to the card [a or b] insertion, the vcc_ok, the crd_vcc value and the current overflow powered to either card [a or b]. the internal register can be read when pgm = high. the logic level is forced to high when the input voltage drops below the v bat min (2.0 v), thus reducing the stand by current, assuming the status pin is not pulled down externally. the associated pullup resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low.
ncn6004a http://onsemi.com 9 pin description (continued) pin description type symbol 47 int output this pin is activated low when a card has been inserted and detected in either of the external ports. the signal is reset by either a positive going transition on pin cs , or by a high level on pin pwr_on combined with cs = low. similarly, an interrupt is generated when either one of the crd_vcc output is overloaded. on the other hand, the pin is forced to a logic high when the input voltage v cc drops below 2.0 v min. the associated pull up resistor is either connected to v cc (en_rpu = h) or disconnected when en_rpu = low. 48 anlg_gnd ground this pin is the ground reference for both analog and digital signals and must be connected to the system ground. care must be observed to provide a copper pcb layout designed to avoid small signals and power transients sharing the same track. good high frequency techniques are strongly recommended. maximum ratings (note 2) rating symbol value unit power supply input supply voltage v cc 6 v v in digital input pins ?0.5 v < v in < v cc +0.5 v, but < 6.0 v v power supply input current iv cc 500 ma digital input pins v in in ?0.5 < v cc or v cc < 5.5 5 v ma digital output pins v out i out ?0.5 < v cc or v cc < 5.5 10 v ma card interface pins v card i card ?0.5v < v card < crd_vcc +0.5v 15 ma (internally limited) v ma esd capability, human body model (note 3) standard pins card interface pins (card a or b) v esd 2 8 kv kv tqfp48 power dissipation @ tab = +85 c thermal resistance junction?to?air p d r j a 800 50 mw c/w operating ambient temperature range t a ?40 to +85 c operating junction temperature range t j ?40 to +125 c maximum junction temperature (note 4) t jmax +150 c storage temperature range ta g ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum electrical ratings are defined as those values beyond which damage(s) to the device may occur at t a = +25 c. 3. human body model, r = 1500 , c = 100 pf. 4. absolute maximum rating beyond which damage(s) to the device may occur.
ncn6004a http://onsemi.com 10 power supply section general test conditions, unless otherwise specified: operating temperature: ?25 c < t a < +85 c, v cc = +3.0 v, crd_vcc_a = crd_vcc_b = +5.0 v. rating symbol pin min typ max unit i out = 2 x 65 ma (both external cards running simultaneously) @ 3.0 v < v cc < 5.5 v crd_vcc 29, 32 4.6 ? 5.4 v i out = 2 x 55 ma per pin (both external cards running) v out defined @ crd_vcc = 3.0 v @ 3.0 v < v cc < 5.5 v crd_vcc 29, 32 2.7 ? 3.3 v i out = 2 x 35 ma per pin (both external cards running) v out defined @ crd_vcc = 1.80 v @ 3.0 v < v cc < 5.5 v crd_vcc 29, 32 1.65 ? 1.95 v output card supply voltage ripple (per crd_vcc outputs) @ : l out = 22 h, l esr < 2.0 , c out = 10 f per crd_vcc (note 5) i out = 35 ma, v out = 1.80 v i out = 55 ma, v out = 3.0 v i out = 65 ma, v out = 5.0 v v ora v orb 29 32 ? ? ? ? ? ? 50 50 50 mv dc/dc dynamic inductor peak current @ v bat = 5.0 v, l out = 22 h, c out = 10 f crd_vcc = 1.8 v crd_vcc = 3.0 v crd_vcc = 5.0 v i ccov 29, 32 ? ? ? 200 280 430 ? ? ? ma standby supply current conditions (note 5): anlg_vcc = pwr_vcc = 3.0 v pwr_on = h, status = h, cs = h card a and card b clock_in = h, i/o = h, reset = h all logic inputs = h, temperature range = 0 c to +50 c anlg_vcc = pwr_vcc = 5.0 v temperature range ?25 c to +85 c all other test conditions identical anlg_vcc = pwr_vcc = 1.8 v temperature range ?25 c to +50 c all other test conditions identical note: this parameter is guaranteed by design, not production tested. i dd 42, 28, 33 ? ? ? ? ? ? ? 20 ? ? 50 ? ? 5.0 ? a operating supply current anlg_vcc = pwr_vcc = 5.5 v @ crd_vcc_a/b = 5.0 v @ crd_vcc_ a/b = 3.0 v @ crd_vcc_ a/b = 1.85 v anlg_vcc = pwr_vcc = 3.3 v @ crd_vcc_a/b = 5.0 v @ crd_vcc_ a/b = 3.0 v @ crd_vcc_ a/b = 1.85 v pwr_on = h, cs = h, clk_a = clk_b = low, all card pins unloaded i ddop 42, 28, 33 0.7 0.7 0.7 0.2 0.2 0.2 ma v bat under voltage detection positive going slope v bat under voltage detection negative going slope v bat under voltage detection hysteresis note: the voltage present in pins 28 and 33 must be equal to or note: lower than the voltage present in pin 42. v batlh v batll v bathy 42 2.1 2.0 ? ? ? 100 2.7 2.6 ? v v mv output continuous current card a or card b (both cards can be operating simultaneously) @ 3.0 < v cc < 5.5 v output voltage = 1.85 v output voltage = 3.0 v output voltage = 5.0 v i ccp 31, 42 35 55 65 ma output over current limit (a or b) v bat = 3.3 v, crd_vcc = 1.8 v, 3.0 v or 5.0 v v bat = 5.0 v, crd_vcc = 1.8 v, 3.0 v or 5.0 v i ccov 31, 42 100 150 ma output over current time out per card i tdoff 31, 42 4.0 ms output card supply turn on time @ l out = 22 f, c out = 10 f ceramic. v cc = 2.7 v, crd_vcc = 5.0 v (a or b) v ccton 31, 42 500 s 5. assuming anlg_vcc and pwr_vcc pins are connected to the same power supply.
ncn6004a http://onsemi.com 11 power supply section general test conditions, unless otherwise specified: operating temperature: ?25 c < t a < +85 c, v cc = +3.0 v, crd_vcc_a = crd_vcc_b = +5.0 v. (continued) rating unit max typ min pin symbol output card supply shut off time @ c out = 10 f, ceramic. v cc = 2.7 v, crd_vcc = 5.0 v, v ccoff < 0.4 v (a or b) v cctoff 31, 42 100 250 s dc/dc converter operating frequency (a or b) f sw 31, 42 600 khz 5. assuming anlg_vcc and pwr_vcc pins are connected to the same power supply. digital input/output section 2.70 < v cc < 5.50 v, normal operating mode (?25 c to +85 c ambient temperature, unless otherwise noted) rating symbol pin min typ max unit a0, a1, a2, a3, card_sel, pwr_on, pgm , cs , mux_mode, en_rpu, reset_a, reset_b, c4_a, c8_a, c4_b, c8_b high level input voltage low level input voltage input capacitance v ih v il c in 1, 2, 3, 4, 5, 6, 7, 8, 44, 45, 10, 18, 11, 12, 16, 17 0.7 * v bat v bat 0.3 * v bat 10 v v pf status, int output high voltage @ i oh = ?10 a output low voltage @ i oh = 200 a v oh v ol 46, 47 v bat ?1.0 v 0.40 v status, int output rise time @ c out = 30 pf output fall time @ c out = 30 pf trsta, trint tfsta, tfint 5 100 s ns clock_a asynchronous input clock @ dc = 50% 1% f clkina 13 40 mhz clock_b asynchronous input clock @ dc = 50% 1% f clkinb 15 40 mhz i/o_a, i/o_b, both directions @ c out = 30 pf i/o rise time i/o fall time t rioa , t riob t fioa , t fiob 9, 19 0.8 0.8 s status pull up resistance r sta 46 35 50 k int pull up resistance r int 47 35 50 k i/o_a pull up resistance r ioa 9 14 20 35 k i/o_b pull up resistance r iob 19 14 20 35 k reset_a pull up resistance r rsta 10 60 100 k reset_b pull up resistance r rstb 18 60 100 k c4_a pull up resistance r c4a 11 60 100 k c8_a pull up resistance r c8a 12 60 100 k c4_b pull up resistance r c4b 17 60 100 k c8_b pull up resistance r c8b 16 60 100 k cs pull up resistance r cs 7 60 100 k crd_det_a and crd_det_b pull up resistance r deta r detb 20 41 500 500 k k
ncn6004a http://onsemi.com 12 card interface section @ 2.70 < v cc < 5.50 v, normal operating mode (?25 c to +85 c ambient temperature, unless otherwise noted) crd_vcc_a = crd_vcc_b = 1.8 v or 3.0 v or 5.0 v rating symbol pin min typ max unit crd_rst_a, crd_rst_b output voltage output rst high level @ irst = ?200 a output rst low level @ irst = 200 a crd_rst_a, crd_rst_b rise and fall time rst rise time @ c out = 30 pf rst fall time @ c out = 30 pf v oh v ol trrst tfrst 23, 38 23, 38 23, 38 23, 38 crd_vcc?0.5 0 crd_vcc 0.4 100 100 v v ns ns crd_clk_a, crd_clk_b output clock output operating clock card a and card b output operating clock dc, card a and card b (input dc = 50%, 1%) note: this parameter is guaranteed by design, functionality 100% tested at production. output operating clock rise time slow mode card a and card b output operating clock fall time slow mode card a and card b output operating clock rise time fast mode card a and card b output operating clock fall time fast mode card a and card b output clock high level, card a and card b, @ iclk = ?200 a output clock low level, card a and card b, @ iclkc = 200 a f clka , f clkb trclka, trclkb tfclka, tfclkb trclka, trclkb tfclka, tfclkb v oh v ol 30, 31 45 crd_vcc?0.5 0 20 55 16 16 4 4 crd_vcc 0.4 mhz % ns ns ns ns v v crd_io_a, crd_io_b data transfer data transfer frequency, card a and card b data rise time, card a and card b, @ c out = 30 pf data fall time, card a and card b, @ c out = 30 pf data output high level, card a and card b @ icrd_io = ?20 a data output low level, card a and card b @ icrd_io = 20 a f ioa , f iob t rioa, t riob t fioa, t fiob v oh v ol 24, 37 crd_vcc?0.5 0 400 0.8 0.8 crd_vcc 0.4 khz s s v v crd_io_a and crd_io_b output voltages i/o_a = i/o_b = 0, i ol = 500 a v ol 24, 37 0.40 v crd_c4_a, crd_c4_b output voltages output c4 high level @ irst = ?200 a output c4 low level @ irst = 200 a crd_c4_a, crd_c4_b rise and fall time c4 rise time @ c out = 30 pf c4 fall time @ c out = 30 pf v oh v ol trc 4 tfc 4 22, 39 crd_vcc?0.5 0 crd_vcc 0.4 100 100 v v ns ns crd_c8_a, crd_c8_b output voltages output c4 high level @ irst = ?200 a output c4 low level @ irst = 200 a crd_c8_a, crd_c8_b rise and fall time c8 rise time @ c out = 30 pf c8 rst fall time @ c out = 30 pf v oh v ol trc 8 tfc 8 21, 40 crd_vcc?0.5 0 crd_vcc 0.4 100 100 v v ns pull up resistance, cs = low, pwr_on = high crd_io_a crd_io_b r ola r olb 24 37 14 14 20 20 35 35 k card detection bias pull up current, card a or card b crd_det_a, crd_det_b i deta i detb 20 41 15 15 a card insertion/extraction negative going input low voltage v ildeta v ildetb 20 41 0 0 0.30 * v bat 0.30 * v bat v card detection insertion/extraction digital filtering delay crd_det_a crd_det_b t dcina t dcinb 20 41 50 50 s card_a or card_b short circuit current: crd_io, crd_rst, crd_c4, crd_c8 crd_clk (according to iso and emv specifications) ishort ishortclk 15 70 ma
ncn6004a http://onsemi.com 13 digital dynamic section normal operating mode rating symbol pin min typ max unit card signal sequence interval, crd_vcc_a and crd_vcc_b: crd_io_a, crd_rst_a, crd_clk_a, crd_c4_a, crd_c8_a crd_io_b, crd_rst_b, crd_clk_b, crd_c4_b, crd_c8_b td seq 24, 23, 30, 37, 38, 31 0.5 0.5 2 2 s internal reset delay td reset 1.0 s internal status delay time td ready 46 1.0 s pwr_on low state pulse width (figure 11), assuming crd_vcc reservoir capacitor = 10 f. t pwrlow 8 5 s pwr_on high state pulse width (figure 11) t pwrset 8 200 ns pwr_on preset delay (figure 11) t pwrpre 5, 7, 8 300 ns pwr_on programming hold time (figure 11) t pwrhold 5, 7, 8 100 ns pwr_on to card_sel change delay time (figure 12) t cseldly 5, 6, 8 100 ns pgm to pwr_on delay time (figure 12) tpgmdly 5, 6, 8 300 ns pwr_on internal set/reset pulses width (figure 12) tpwrp 8 20 ns digital dynamic section programming mode rating symbol pin min typ max unit data set?up time, time reference = pgm , a0, a1, a2, a3, card_sel, and cs . data signal rise and fall time t smod t smodtr 8, 46, 1, 2, 3, 4, 5, 6 100 50 ns ns data hold time, time reference = pgm , a0, a1, a2, a3, card_sel, and cs . t smod t smodtr 8, 46, 1, 2, 3, 4, 5, 6 100 50 ns ns chip select cs low state pulse width cs signal rise and fall time t wcs t rfcs 7 300 50 ns ns
ncn6004a http://onsemi.com 14 programming and status functions the ncn6004a includes a programming interface and a status interface. figure 4 illustrates the sequence one must follow to enter and exit the programming mode. table 1 and table 2 provide the logical functions associated with the input and output signals. the parameters are latched upon the rising edge of the pgm signal, the cs pin being held low. any number of programming sequences can be performed while the cs pin is low, but the minimum timings must be observed. a0 a1 a2 a3 card_sel parameters are latched upon pgm rise slope figure 4. programming sequence t sprg t wcs t hprg pgm cs example: set crd_vcc_a = 3.0 v example: set crd_clk_b = 1/8 on the other hand, since the programming data are latched upon the rising edge of the pgm signal, the most up to date selected card (using card_sel = h or l) is used to activate the associated card. consequently, when both cards must be updated with the same programmed content, a dual pgm sequence must be carried out, changing the card_sel signal during the high level state of the pgm pin. although selecting a card in possible during the same chip select sequence (as depicte d here above), the user must make sure that no data will be present to a card not ready for such a function. as a matter of fact, all the card signals are routed to the selected card immediately after a card_sel change, the ncn6004a taking no further logic control prior to activate the swap. to avoid any risk, one can run a sequence with the selected card, return cs to high, change the card_sel according to the expected card selection, and pull cs to low to activate the selected card. table 1. programming and reading basic functions pin name select #a #b select v cc on/off program clock_in poll card status #a or #b poll i cc overload #a or #b anlg_vcc input voltage ok 7 cs 0 0 0 0 0 0 46 status ? ? ? read read read 1 a0 0/1 0/1 0/1 1 0 0 2 a1 0/1 0/1 0/1 1 1 0 3 a2 0/1 0/1 0/1 x x x 4 a3 0/1 0/1 0/1 x x x 5 card_sel 0/1 0/1 0/1 0/1 0/1 0/1 6 pgm 0/1 0/1 0/1 1 1 1
ncn6004a http://onsemi.com 15 table 2. programming functions (conditions at start?up are in bold ) (hex) pgm a3 a2 a1 a0 card_sel crd_v cc #a crd_vcc #b crd_clk #a crd_clk #b crd_det #a crd_det #b clock slope 00 0 0 0 0 0 1 1.80 v ? ? ? ? ? ? 01 0 0 0 0 1 1 3.0 v ? ? ? ? ? ? 02 0 0 0 1 0 1 5.0 v ? ? ? ? ? ? 03 0 0 0 1 1 1 ? ? ? ? ? slow 00 0 0 0 0 0 0 ? 1.80 v ? ? ? ? ? 01 0 0 0 0 1 0 ? 3.0 v ? ? ? ? ? 02 0 0 0 1 0 0 ? 5.0 v ? ? ? ? 03 0 0 0 1 1 0 ? ? ? ? ? ? slow 04 0 0 1 0 0 1 ? ? 1/1 ? ? ? 05 0 0 1 0 1 1 ? ? 1/2 ? ? ? ? 06 0 0 1 1 0 1 ? ? 1/4 ? ? ? ? 07 0 0 1 1 1 1 ? ? 1/8 ? ? ? 04 0 0 1 0 0 0 ? ? ? 1/1 ? ? ? 05 0 0 1 0 1 0 ? ? ? 1/2 ? ? ? 06 0 0 1 1 0 0 ? ? ? 1/4 ? ? ? 07 0 0 1 1 1 0 ? ? ? 1/8 ? ? ? 08 0 1 0 0 0 1 ? ? start ? ? ? ? 09 0 1 0 0 1 1 ? ? stopl ? ? ? ? 0a 0 1 0 1 0 1 ? ? stoph ? ? ? ? 0b 0 1 0 1 1 1 ? ? ? ? ? ? fast 08 0 1 0 0 0 0 ? ? ? start ? ? ? 09 0 1 0 0 1 0 ? ? ? stopl ? ? ? 0a 0 1 0 1 0 0 ? ? ? stoph ? ? ? 0b 0 1 0 1 1 0 ? ? ? ? ? ? fast 0c 0 1 1 0 0 1 ? ? ? ? no ? ? od 0 1 1 0 1 1 ? ? ? ? nc ? 0c 0 1 1 0 0 0 ? ? ? ? ? no ? 0d 0 1 1 0 1 0 nc ? 0e 0 1 1 1 0 1 ? ? clk_d_a ? ? ? ? 0f 0 1 1 1 1 1 ? ? clk_d_b ? ? ? ? 0e 0 1 1 1 0 0 ? ? ? clk_d_b ? ? ? 0f 0 1 1 1 1 0 ? ? ? clk_d_a ? ? ?
ncn6004a http://onsemi.com 16 table 3. status pins data state (hex) pgm a3 a2 a1 a0 card_sel status #a status #b 00 1 x x 0 0 x vcc_v bat _ok pass = low vcc_ok fail = high 01 1 x x 0 1 1 crd_vcc_a in range pass = high fail =low 02 1 x x 1 0 1 crd_vcca overloaded pass = high fail = low 03 1 x x 1 1 1 crd_det_a card present = high 00 1 x x 0 0 x vcc_ok pass = low vcc_ok fail = high 01 1 x x 0 1 0 crd_vcc_b in range pass = high fail =low 02 1 x x 1 0 0 crd_vcc_b overloaded pass = high fail = low 03 1 x x 1 1 0 crd_det_a card present = high *the status register is not affected when the ncn6004a operates in any of the programming mode. initialized conditions upon start?up are depicted by bold characters in table 2 and table 4. vbat 2.10 v 2.00 v 2.70 v 3.30 v vbat_ok vbat status max. anlg_vcc under voltage min. anlg_vcc under voltage typical anlg_vcc operating voltage the input power supply voltage monitoring applies to the card selected. figure 5. reading anlg_vcc status (monitoring anlg_vcc input voltage) system states upon upon start?up table 4. operating conditions upon start?up crd_vcc_a 3.0 v crd_vcc_b 3.0 v crd_clk_a 1/1 ratio crd_clk_b 1/1 ratio crd_clk_a start (clock is valid) crd_clk_b start (clock is valid) crd_clk_a low speed slope crd_clk_b low speed slope clock route direct (clk_a a, clk_b b) depending upon the logic state at turn on present on pin 44, the system will run into a parallel mode (mux_mode = l) or a multiplexed mode (mux_mode = h). it is not possible to change the logic state once the system is running. similarly, depending upon the logic state present pin 45, the internal pull up resistors (i/o_a and i/o_b line) will be either connected to anlg_vcc voltage (en_rpu = h) or disconnected (en_rpu = l). it is not possible to change this operating condition once the system is running.
ncn6004a http://onsemi.com 17 parallel/mulitplexed operation modes the logic input mux_mode, pin 44, provides a way to select the operation mode of the ncn6004a. depending upon the logic level, the device operates either in a parallel mode (all the card pins, on the p side, are fully independent) or in multiplexed mode (all the logic card pins, on the p side, share a common bus). figure 6 shows a simplified schematic of the multiplex circuit built in the ncn6004a chip. figure 6. simplified mux_mode logic and multiplex circuit 13 10 11 12 9 19 18 17 16 15 reset_a c4_a c8_a clk_in_a i/o_a i/o_b c8_b c4_b rest_b clk_in_b 15 15 mux_mode card_sel card_a gating buffers buffers buffer buffer buffer card_b gating i/o_a buffer i/o_b card_b card_a clk_a q1 q2 clk_b q3 a a a b b b clock dividers 23 22 21 24 37 38 39 40 30 31 q4 multiplexer & multiplexer in both case, the device is programmed by means of the common logic controls pins (a0, a1, a2, a3, pgm , pwr_on, card_sel and cs ). on the other hand, the logic status returned by the interface (status pin 46) is shared by the two channels and can be read independently by setting card_sel accordingly. the card related signals connected on the c side are multiplexed or independent, depending upon the mux_mode state as described here below. mux_mode = low parallel mode when pin 44 is low, the device operates in the parallel mode. the transfer gate q4 and the multiplexer circuit are disconnected and all the data will be carried out through their respective paths. the switches q1, q2 and q3 are flipped to the b position, thus providing a direct connection from port b control signals to card_b all the card_a and card_b signals are independent and both cards can operate simultaneously, the data transaction can take place at the same time and processed independently. of course, the microcontroller must have the right data bus available to handle this process. however, it is not possible to change the operating mode once the system has been started. if such a function is needed, one must pull down the related ncn6004a power supply, change the mux_mode logic level, and re?start the interface. mux_mode = high multiplexed mode when pin 44 is high, the device operates in a multiplexed mode and all the card signals are shared between card_a and card_b, except the input clocks which are independent at any time. the rst_b, c4_b and c8_b pins are preferably left open at pcb level. the i/o_b pin must be left open and cannot be connected to any external signal or bias voltages. the transfer gate q4 is switched on and, depending upon the card_sel logic level, the i/o data will be transferred
ncn6004a http://onsemi.com 18 to either card_a or card_b. it is neither possible to connect directly i/o_a to i/o_b nor to connect the i/o_b pin to ground or voltage supply. the multiplexer is activated and the card_sel signal is used to select the card in use for a given transaction. the switches q1, q2 and q3 and swapped to the a position, thus providing a path for the control signals applied to the card_a side. when the card_sel signal flips from one card to the other, the previous logic states of the on going card are latched in the chip and the related output card pin are maintained at the appropriate levels. when the system resumes to the previous card, the latches return to the transparent operation and the signals presented by the p take priority over the previously latched states. on the other hand, the input clocks (clk_in_a and clk_in_b) are maintained independent and can be routed to either card_a or card_b according to the programming functions given in table 2. card power supply timing when the pwr_on signal is high, the associated crd_vcc_a or crd_vcc_b power supply rise time depends upon the current capability of the dc/dc converter together with the external inductors l1/l2 and the reservoir capacitor connected across each card power supply pin and ground. on the other hand, at turn off, the crd_vcc_a and crd_vcc_b fall times depend up on the external reservoir capacitor and the peak current absorbed by the internal nmos device built across each crd_vcc_a/ crd_vcc_b and ground. these behaviors are depicted by figure 7, assuming a 10 f output capacitor. since none of these parameters can have infinite values, the designer must take care of these limits if the t on or the t off provided by the data sheets does not meet his requirement. t v crd_vcc = 5 v crd_vcc = 4.75 v crd_vcc = 0.40 v turn on shut off 500 s max 250 s max figure 7. card power supply turn on and shut off typical timings power down operation the power down mode can be initiated by either the external mpu or by the internal error condition. the communication session is terminated immediately, according to the iso7816?3 sequence. on the other hand, the mpu can run the stand by mode by forcing cs = h, leaving the chip in the previous operating mode. when the card is extracted, the interface will detect the operation and will automatically run the power down sequence of the related card as described by the iso/cei 7816?3 sequence depicted in figure 8 and illustrated by the oscillogram in figure 9. crd_vcc crd_rst crd_clk crd_io card extraction detected t crd_c4 crd_c8 crd_det internal delay 400 ns typ. figure 8. card power down sequence force rst to low force clk to low, unless it is already in this state force c4 and c8 to low force crd_io to low shut off the crd_vcc supply
ncn6004a http://onsemi.com 19 on the other hand, the power down sequence is automatically activated when the v bat voltage drops below the vcc_ok level, regardless of the logic conditions present on the control pins, or when the related crd_vcc_x output voltage reaches the overload condition. figure 9. power down sequence figure 10. power down sequence: timing details
ncn6004a http://onsemi.com 20 card detection the card detector circuit provides a constant low current to bias the crd_det_a and crd_det_b pins, yielding a logic high when no card is present and the external switch is normally open type. the internal logic associated with pins 20 and 41 provides a programmable selection of the slope card detection. the transition is filtered out by the internal digital filter circuit, avoiding false interrupt. in addition to the typical 50 s delay, the mpu shall provide an additional delay to cope with the mechanical stabilization of the card interface (typically 1 ms), prior to valid the crd_vcc_a or crd_vcc_b supply. when a card is inserted, the detector circuit asserts int = low as depicted before, the external p being responsible to clear the interrupt signal, taking the necessaries actions. when the ncn6004a detects a card extraction, the power down sequence is automatically activated for the related interface section, regardless of the pwr_on state, and the int pin is asserted low. it is up to the external mpu to clear this interrupt by pulsing the cs pin. crd_det_a status a0 a1 interrupt card identification clear interrupt card present: status = 1 card not present: status = 0 card extracted 50 s < t < 150 s high high high 50 s < t < 150 s clear interrupt a2 a3 card_sel high = card a irrelevant irrelevant figure 11. typical interrupt sequence pgm int cs acknowledge & processing the interrupt signal can be cleared either by a positive going slope on the chip select pin as depicted in figure 11, or by forcing the pwr_on signal high (keeping cs = low) for the related card. the polarity of the card detection switch can be either normally open or normally close and is software controlled as defined here below and in table 2. table 5. card detection polarity cs pgm a3 a2 a1 a0 card_sel crd_det_a crd_det_b 1 x x x x x x qn ?1 qn ?1 0 1 x x x x x qn ?1 qn ?1 0 0 1 1 0 0 1 normally open qn ?1 0 0 1 1 0 1 1 normally close qn ?1 0 0 1 1 0 0 0 qn ?1 normally open 0 0 1 1 0 1 0 bn ?1 normally close *the polarity change is validated upon the next positive pgm transient.
ncn6004a http://onsemi.com 21 power management the main purpose of the power management is to provides the necessary output voltages to drive the 1.80 v, 3.0 v or 5.0 v smart card types. on top of that, the dc/dc converter efficiency must absorb a minimum current on the v bat supply. beside the power conversion, in the stand by mode (pwr_on = l), the power management provides energy to the card detection circuit only. all the card interface pins are forced to ground potential, saving as much current as possible out of the battery supply. in the event of a power up request coming from the external mpu (card_sel =h/l, pwr_on = h, cs = l), the power manager starts the dc/dc converter related to the selected interface section. when the selected section (either crd_vcc_a or crd_vcc_b) voltage reaches the programmed value (1.8 v, 3.0 v or 5.0 v), the circuit activates the card signals according to the following sequence: crd_vcc_x crd_io_x crd_c4_x crd_c8_x crd_clk_x crd_rst_x the logic level of the data lines are asserted high or low, depending upon the state forced by the external mpu, when the start?up sequence is completed. under no situation the ncn6004a shall automatically launch a smart card atr sequence. at the end of the transaction, asserted by the mpu (card_sel = h/l, pwr_on = l, cs = l), or under a card extraction, the iso7816?3 power down sequence takes place: crd_rst_x crd_clk_x crd_c4_x crd_c8_x crd_io_x crd_vcc_x when cs = h, the bi?directional i/o lines (pins 9 and 19) are forced into the high impedance mode to avoid signal collision with any data coming from the external mpu. output voltage programming the internal logic provides a reliable circuit to activate any of the dc/dc converters safely. in particular, the turn on/turn off of these converters is edge sensitive and controlled by the rising/falling edges of the pwr_on signal applied with chip select pin low. the card_sel signal is used to select either crd_vcc_a or crd_vcc_b as defined by the functions programming in table 2. pwr_on crd_vcc rise time crd_vcc no change crd_vcc_a pwr down vcctoff card_sel crd_vcc_a crd_vcc_b set reset vccton vccton see note note : minimum 1 ms delay before to send a power off command to the same selected output is recommended. figure 12. card power supply controls cs although it is possible to change the output voltage straightly from 5.0 v to 1.80 v, care must be observed as the stabilization time will be relatively long if no current is absorbed from the related output pin. according to the typical sequence depicted, it is not possible to program simultaneously the two dc/dc converters, but two separate sequences must take place. on top of that, since the circuit is edge sensitive, the pwr_on signal must present such a transient when a given state is expected for the converter. the pwr_on and cs timings definitions are given in figure 13.
ncn6004a http://onsemi.com 22 pwr_on tpwrhold tpwrlow card_sel set reset tpwrpre tpwrset tpwrp note: tpwrset: this delay is necessary to latch?up the pwr_on condition and does not represent the crd_vcc output voltage rise time. tpwrlow: this delay includes the internal iso7816?3 power down sequence to make sure the dc/dc converter is fully deactivated. figure 13. power on sequence timings cs pwr_on tpgmdly card_sel tcseldly tpwrw programming chip selected tpwrhold note: tpwrw: this delay represents the minimum pulse width needed to write the pwr_on status into the associated dc/dc latch figure 14. power on and card_sel sequence timings sequence cs pgm dc/dc converter the power conversion is carried out either in step up or step down mode. the operation is fully automatic and, beside the output voltage programming, does not need any further adjustments. the simplified dc/dc converter, given in figure 15, is based on a full bridge structure capable to handle either step up or step down power supply using an external inductor. this structure brings the capability to operate from a wide range of input voltage, while providing the accurate 1.80 v, 3.0 v or 5.0 v requested by the smart cards. beside the accuracy, the major aim of this structure is the high efficiency necessary to save energy taken from the battery. on the other hand, using two independent converters provides a high flexibility and prevent a total system crash in the event of a failure on one of the card connected to the interface. operation note: described operation makes reference to card_a and can be applied to card_b. the system operates with a two cycles concept: 1. cycle 1: q15 and q4 are switched on and the inductor l1 is charged by the energy supplied by the external battery. during this phase, the pairs q1/q16 and q2/q3 are switched off. the current flowing into the two mosfet q1 and q4 is internally monitored and will be switched off when the ipeak value (depending upon the programmed output voltage value) is reached. at this point, cycle 1 is completed and cycle 2 takes place. the on time is a function of the battery voltage and the value of the inductor network (l and zr) connected across pins 26/27 and 34/35. a 4 s time out structure makes sure the system does run in a continuous cycle 1 loop. 2. cycle 2: q1 and q16 are switched on and the energy stored into the inductor l1 is dumped into the external load through q16. during this phase, the pair q15/q4 and the pair q2/q3 are switched off. the current flow period is constant (900 ns typical) and cycle 1 repeats after this time if the crd_vcc voltage is below the specified value.
ncn6004a http://onsemi.com 23 when the output voltage reaches the specified value (1.80 v or 3.0 v or 5.0 v), q1 and q16 are switched off immediately to avoid over voltage on the output load. in the mean time, the two extra nmos q2 and q3 are switched on to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over the system. figure 16 illustrates the theoretical basic waveforms present in the dc/dc converter. the control block gives the logic states according to the bits provided by the external p. these controls bits are applied to the selected dc/dc converter to generate the programmed output voltage. the mos drive block includes the biases necessaries to drive the nmos and pmos devices as depicted in the block diagram given figure 15. u1 r2 r3 r4 vref logic control # a v0 pwr_on overload vcc_ok voltage regulation gnd vcc vref_1.8/3/5 v pgm card_sel a0 a1 a2 dc/dc multiplexed controls pwr_on a3 q1 q4 q15 q16 l1 c1 vcc pwr_gnd crd_vcc_a gnd gnd mixed logic / analog block g_q1 g_q2 g_q3 g_q4 g_hiz gnd g_q7 q3 q2 q5 v1 vout r1 q7 q6 5.0 v 5.0 v gnd figure 15. basic dc/dc converter diagram cs 10 f c2 gnd 10 f gnd 22 h 29 27 26 25 28 u2 r6 r7 r8 vref logic control # a v0 pwr_on overload vcc_ok voltage regulation gnd vcc vref_1.8/3/5 v q8 q11 q17 q18 l2 c3 vcc pwr_gnd crd_vcc gnd gnd mixed logic / analog block g_q1 g_q2 g_q3 g_q4 g_hiz gnd g_q7 q10 q9 q12 v1 vout r5 q14 q13 3.0 v 5.0 v gnd 10 f c4 gnd 10 f gnd 22 h 32 34 35 36 33
ncn6004a http://onsemi.com 24 since the output inductor l1 and the reservoir capacitor c1 carry relative high peak current, low esr devices must be used to prevent the system from poor output voltage ripple and low ef ficiency. using ceramic capacitors, x5r or x7r type, are recommended, splitting the 10 f in two separate parts when there is a relative long distance between the crd_vcc_x output pin and the card vcc input. on the other hand, the inductor shall have an esr below 1.0 to achieve the high efficiency over the full temperature range. however, inductor with 2.0 esr can be used when a slight decrease of the efficiency is acceptable at system level. ton toff crd_vcc charged charge crd_vcc next crd_vcc charge q1 / q4 q2 / q3 il (time is not to scale) crd_vcc crd_vcc voltage regulated ipeak vripple q5/q6 figure 16. theoretical dc/dc operating when the crd_vcc is programmed to zero volt, or when the card is extracted from the socket, the active pull down q5 rapidly discharges the output reservoir capacitor, making sure the output voltage is below 0.40 v when the card slides across the contacts. based on the experiments carried out during the ncn6004a characterization, the best comprise, at time of printing this document, is to use two 4.7 f/10 v/ceramic/x7r capacitor in parallel to achieve the crd_vcc filtering. the esr will not extend 50 m over the temperature range and the combination of standard parts provide an acceptable ?20% to +20% tolerance, together with a low cost. table 6 shows a quick comparison between the most common type of capacitors. obviously, the capacitor must be smd type to achieve the extremely low esr and esl necessary for this application. figure 17 illustrates the crd_vcc ripple observed in the ncn6004a demo board running with x7r ceramic capacitors. table 6. ceramic/electrolytic capacitors comparison manufacturer type/series format max value tolerance typ. z @ 500 khz murata ceramic/grm225 0805 10 f/6.3 v ?20% /+20% 30 m murata ceramic/grm225 0805 4.7 f/6.3 v ?20% /+20% 30 m vishay tantalum/594c/593c 1206 10 f/16 v 450 m vishay electrolytic/94sv 1812 10 f/10 v ?20%/+20% 400 m miscellaneous electrolytic low cost 1812 10 f/10 v ?35%/+50% 2.0
ncn6004a http://onsemi.com 25 figure 17. typical crd_vcc ripple voltage note: operating conditions under full output load. figure 18. typical card voltage turn on and start?up sequence figure 19. typical card supply turn off 58 60 62 64 66 68 70 72 74 2.5 3.0 3.5 4.0 4.5 5.0 5.5 figure 20. crd_vcc efficiency as a function of the input supply voltage v bat (v) eff (%) v out = 1.8 v v out = 5.0 v v out = 3.0 v l out = 22 h esr = 2 the curves in figure 20, illustrate the typical behavior under full output current load (35 ma, 60 ma and 65 ma), according to emv specifications. during the operation, the inductor is subject to high peak current as depicted in figure 21 and the magnetic core must sustain this level of current without damage. in particular, the ferrite material shall not be saturated to avoid uncontrolled current spike during the charge up cycle. moreover, since the dc/dc efficiency depends upon the losses developed into the active and passive components, selecting a low esr inductor is preferred to reduce these losses to a minimum.
ncn6004a http://onsemi.com 26 figure 21. typical output voltage ripple test conditions: input v cc voltage = 5.0 v, current = 200 ma /div, t amb = +20 c according to the iso7816?3 and emv specifications, the interface shall limits the crd_vcc output current to 200 ma maximum, under short circuit conditions. the ncn6004a supports such a parameter, the limit being depending upon the input and output voltages as depicted in figure 22. figure 22. output current limit figure 23. output current limit as a function of the temperature 180 160 140 120 100 80 60 40 20 0 6 5 4 3 2 v bat (v) i out (ma) v o = 5.0 v v o = 3.0 v v o = 1.8 v 100 ?5.0 ?25 temperature ( c) 15 35 55 75 95 11 5 160 150 140 130 120 110 i out (ma) v o = 5.0 v v o = 3.0 v v o = 1.8 v i o(max) = f(v bat ) beside the continuous current capability, the smart card power supply must be capable of providing a 100 ma pulsed current during the data transaction. the iso7816?3, paragraph 4.3.2, defines this 400 ns pulse as a function of the environment. as a matter of fact, this pulse does not come solely from the ncn6004a dc/dc converter, but the reservoir capacitor and the associated pcb tracks shall be considered as well.
ncn6004a http://onsemi.com 27 clock divider the main purpose of the built in clock generator is four folds: 1. adapts the voltage level shifter to cope with the different voltages that might exist between the mpu and the smart card 2. provides a frequency division to adapt the smart card operating frequency from the external clock source. 3. control the clock state according to the smart card specification. 4. provides an input clock re?routing to route the clock_in_a and clock_in_b signals to either crd_clk_a or crd_clk_b output pins. in addition, the ncn6004a adjusts the signal coming from the microprocessor to get the duty cycle window as defined by the iso7816?3 specification. the logic input pins card_sel, a0, a1, pgm , i/o and reset fulfill the programming functions when both pgm and cs are low. the clock input stage (clock_in) can handle a 40 mhz frequency maximum, the divider being capable to provide an 1:8 ratio. of course, the ratio must be defined by the engineer to cope with the smart card considered in a given application and, in any case, the output clock (crd_clk_a and crd_clk_b) shall be limited to 20 mhz maximum when the system is considered to operate over the full temperature range. a2 a0 a1 pgm cs clock_in_b 1 2 3 crd_clk_a level shifter & control crd_vcc_a card_a & card_b clock crd_vcc_a a2 card_sel crd_clk_b level shifter & control crd_vcc_b card_a card_b dc/dc block_a crd_vcc_b dc/dc block_b clock_in_a clock_a divider clock_ab divider mux_a&b mux_a&b logic control figure 24. simplified frequency divider and programming functions in order to avoid any duty cycle out of the frequency smart card iso7816?3 and emv specifications, the clock divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, regardless of the divider ratio. consequently, the output crd_clk_a or crd_clk_b frequency division can be delayed by eight clock_in pulses and the microcontroller software must take this delay into account prior to launch a new data transaction.
ncn6004a http://onsemi.com 28 crd_clk clock_in clock : 2 clock : 4 clock : 8 a0 a1 a2 a3 clock is updated upon clock :8 rising edge these bits program internal clock divider clock programming is activated by the pgm rising edge. clock = 1:1 ratio card_sel figure 25. clock programming timings cs pgm the example given in figure 25 highlights the delay coming from the internal clock duty cycle re?synchronization. since the clock signal is asynchronous, it is up to the programmer to make sure the next card transaction is not activated before, respectively, either the crd_clk_a or crd_clk_b signal has been updated. generally speaking, such a delay can be derived from the maximum clock frequency provided to the interface. figure 26. card clock 1/2 divider operation
ncn6004a http://onsemi.com 29 figure 27. clock divider: 8 to 1 operation figure 28. clock divider timing details figure 29. clock divider: run to stop high operation
ncn6004a http://onsemi.com 30 the input clock a and b can be re routed to either crd_clk_a or crd_clk_b output pins by using the programming function as defined in table 2 and table 7. the clock signals can have any frequency value necessary to handle a given type of card (asynchronous or synchronous). these clock signals can be mul tiplexed at any time, but the system must be locked in a safe state prior to make such a change. in particular, the designer must make sure that a and b cards can support such a hot change prior to change the related clocks. table 7. programming clock routing state cs pgm a3 a2 a1 a0 card_sel crd_clk_a crd_clk_b 0e 0 0 1 1 1 0 1 clk_d_a ? default 0f 0 0 1 1 1 1 1 clk_d_b ? ? 0e 0 0 1 1 1 0 0 ? clk_d_b default 0f 0 0 1 1 1 1 0 ? clk_d_a ? on the other hand, the slope of the crd_clk_x signal can be set to either fast or slow, depending upon the frequency of the output clock. this selection is achieved by programming the chip according to table 8. table 8. output clock slope selection state cs pgm a3 a2 a1 a0 card_sel clock slope $03 0 0 0 0 1 1 1 slow default $0b 0 0 1 0 1 1 1 fast ? $03 0 0 0 0 1 1 0 slow default $0b 0 0 1 0 1 1 0 fast ? figure 30. typical rise and fall time in fast and slow operating mode parallel operation when two or more ncn6004a parts operate in parallel on a common digital bus, the chip select pin allows the selection of one chip from the bank of the paralleled devices. of course, the external mpu shall provide one unique cs line for each of the ncn6004a considered interface. when a given interface is selected by cs = l, all the logic inputs becomes active, the chip can be programmed or/and the external card can be accessed. when cs = h, all the input logic pins are in the high impedance state, thus leaving the bus available for other purpose. the pull up resistors connected on each logic input lines on the mpu side (see block diagram in figure 30), can be either activated (connected to v cc ) or disconnected, depending upon the logic state present at en_rpu, pin 45. when these resistors are disconnected, it is the system responsibility to set up the external pull up resistors according to the application?s requirements. when the device operates in the multiplexed mode (mux_mode = high), the internal card #b pull up resistors are connected to v cc , regardless of the en_rpu logic state. on the other hand, when cs = h, the crd_io and crd_rst hold the previous i/o and reset logic state, the crd_clk being either active or stopped and the crd_vcc output voltage will maintain is previous value, according to the programmed state forced by the mpu.
ncn6004a http://onsemi.com 31 figure 31. parallel operation wiring mux_mode = low 13 10 11 12 9 19 18 17 16 15 reset_a c4_a c8_a clk_in_a i/o_a i/o_b c8_b c4_b reset_b clk_in_b 44 5 mux_mode card_sel buffers buffers buffer buffer buffer i/o_a buffer i/o_b card_b card_a clk_a clk_b 23 22 21 24 37 38 39 40 30 31 clock gen. clock gen. multiplex & clock divider card gnd logic control port a port b ctl micro controller when the chip operates in the parallel mode, all the logic signals must be independently controlled by the microcontroller as depicted in figure 31. the mux_mode pin must be hardwired to vcc and it cannot be changed during an operation of the chip. beside this parameter, the user must select to force or not the internal pull up resistors as defined by the en_rpu logic state. figure 32. multiplexed operation wiring mux_mode = high 13 10 11 12 9 19 18 17 16 15 reset_a c4_a c8_a clk_in_a i/o_a i/o_b c8_b c4_b reset_b clk_in_b 44 5 mux_mode card_sel buffers buffers buffer buffer buffer i/o_a buffer i/o_b card_b card_a clk_a clk_b 23 22 21 24 37 38 39 40 30 31 clock gen. clock gen. port a port b ctl micro controller multiplex & clock divider card vcc logic control in the multiplexed mode, the microprocessor card_b side pins are not connected, the logic signals and the i/o line being shared with card_a associated with the crd_sel control bit: figure 32. a key point is to make sure there is no connection associated with the i/o_b pin since this pin is internally shared with the i/o line transaction. the clk_in_a and clk_in_b signals are independent and can be routed to any of the card thanks to the built?in clock multiplexer. data i/o level shifter the built in structure provides a level shifter on each card output signals, the i/o line being driven differently as depicted in figure 33. since the ncn6004a can operate in either a multiplexed or parallel mode, provisions have been made to route the i/o_a input pin to either card_a or card_b. in both case, the i/o pins are driven by an open drain structure with a 20 k pull up resistor as shown figure 33. to achieve the 0.80 s maximum rise time requested by the emv specifications, an accelerator circuit is added on both side of each i/o line. these pulsed circuits yield boost current to charge the stray capacitance, thus accelerating the positive going slope of the i/o signal. on the other hand, the active pull down nmos device q5 provides a low impedance to ground during the battery up and dc/dc start?up phase, avoiding any uncontrolled voltage spikes on the i/o lines.
ncn6004a http://onsemi.com 32 mux_mode = low parallel operation the bi?directional switch q9 is off and the i/o signals are routed straightforward to their appropriate outputs. the two i/o lines can operate simultaneously, depending upon the p capabilities, regardless of the card_sel signal logic level. the pull up resistors, on the p side of each i/o line, can be connected or not as defined by the en_rpu signal. mux_mode = high multiplexed operation the bi?directional switch q9 is on and the i/o_a pin is used to handle data for card_a and card_b. the signal is routed to the appropriate card by means of the card_sel logic signal. in this mode, the i/o_b pin 19 must be left open since the internal data signal will be present on this pin. moreover, since r1 and r3 are in parallel, the pull up resistor r1 is automatically disconnected to maintain the i/o line impedance to 20 k (typical), what ever be the en_rpu logic level. this feature makes sure the current flowing trough the external card is limited to 500 a during a low level state. 24 crd_i/o_a bi?directionnal data transfert 42 anlg_vcc crd_vcc_a 9 29 i/o_a i/o_b crd_i/o_b q1 q2 q3 q5 gnd control logic 37 19 bi?directionnal data transfert q6 q11 q7 q10 control logic card_sel pwr_on 5 44 32 crd_vcc_b mux_mode 45 en_rpu q9 q10 q11 r1 r2 r4 q4 q8 & level shifter & level shifter crd_vcc_a anlg_vcc figure 33. dual bi?directional i/o line level shifter and multiplex r3 gnd crd_vcc_b anlg_vcc cs 7 8 6 pgm
ncn6004a http://onsemi.com 33 note: both sides of the interface run with open drain load (worst case condition) figure 34. typical i/o rise and fall time esd protection the ncn6004a includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed across these pins, the built in structures have been designed to handle either 2 kv, when related to the microcontroller side, or 8 kv when connected with the external contacts. practically, the crd_rst, crd_clk, crd_io, crd_c4 and crd_c8 (both a and b sections) pins can sustain 8 kv, the maximum short circuit current being limited to 15 ma. the crd_vcc_a and crd_vcc_b pins have the same esd protection, but can source up to 65 ma continuously each, the absolute maximum current being 150 ma per section. security features in order to protect both the interface and the external smart card, the ncn6004a provides security features to prevent catastrophic failures as depicted here after. pin current limitation: in case of a short circuit to ground, the current forced by the device is limited to 10 ma for any pins, except crd_clk_a and crd_clk_b pins which are both limited to 70 ma. no feedback is provided to the external mpu. dc/dc operation: the internal circuit continuously senses the crd_vcc_a and crd_vcc_b voltages and, in the case of either over or under voltage situation, update the status register accordingly. this register can be read out by the mpu but no interrupts are activated. dc/dc overload: when an overload is sensed across the crd_vcc_a or crd_vcc_b output, during either the power on sequence or when the system was previously running, the ncn6004a generates an interrupt by pulling down the int pin. it is up to the microcontroller to identify the origin of the overload by reading the status pin accordingly. battery voltage: both the positive going and the negative going voltage are detected by the ncn6004a, a power_down sequence and the sta tus register being updated accordingly. the external mpu can read the status pin to take whatever is appropriate to cope with the situation. the ncn6004a does not provide any further internal voltage regulation.
ncn6004a http://onsemi.com 34 test board schematic diagram 1 tp1 det_b r2 4.7 k r1 4.7 k 1 2 4 3 s1 switch 1 2 j3 clk_a 1 2 j8 clk_b 1 tp6 rst_b 1 tp2 clk_b 1 tp3 c4_b 1 tp4 c8_b 1 tp5 io_b 1 tp12 det_a 1 tp7 rst_a 1 tp8 clk_a 1 tp10 c8_a 1 tp9 c4_a 1 tp11 io_a c12 cs 7 pwr_on 8 status 46 a0 1 a1 2 card_sel 5 pgm 6 i/o_a 9 reset_a 10 c4_a 11 c8_a 12 clk_in_a 13 pwr_vcc_a 28 pwr_gnd 36 crd_det_a 20 crd_vcc_a 29 crd_clk_a 30 crd_io_a 24 crd_det_b 41 crd_vcc_b 32 crd_clk_b 31 crd_io_b 37 crd_rst_a 23 crd_rst_b 38 l2a 27 l1a 26 l1b 34 l2b 35 a2 3 a3 4 en_rpu 45 crd_c4_a 22 crd_c8_a 21 crd_c4_b 39 crd_c8_b 40 pwr_vcc_b 33 pwr_gnd 25 mux_mode 44 int 47 anlg_gnd 14 anlg_gnd 48 anlg_vcc 42 anlg_gnd 43 clk_in_b 15 c8_b 16 c4_b 17 reset_b 18 i/o_b 19 u1 ncn6004 i/o 7 swa 10 swb 9 c4 4 clk 3 rst 2 vcc 1 gnd 5 vpp 6 c8 8 iso7816 j2 smartcard_b i/o 7 swa 10 swb 9 c4 4 clk 3 rst 2 vcc 1 gnd 5 vpp 6 c8 8 iso7816 j12 smartcard_a + c11 100 nf, x7r + c7 4.7uf, x7r + c5 + c6 + c8 r15 10 k r12 1.5 k r11 1.5 k r14 10 k r13 1.5 k r10 1.5 k r16 0r c10 c_clk_b c9 r17 0r c13 220 nf c14 220 nf 1 tp20 a0 1 tp21 a1 1 tp19 a2 tp18 a3 1 tp17 card_sel 1 tp16 pgm 1 tp15 cs 1 tp23 status 1 tp24 int 1 tp22 pwr_on 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 j1 control & i/o r4 1.5k r5 1.5k vcc vcc gnd gnd gnd vcc gnd gnd gnd vcc vcc vcc vcc 1 2 3 4 5 6 7 8 9 r3 8x10k gnd 1 2 j5 mpu_clk 1 2 j7 ext_clk gnd 1 2 j4 mpu_clk 1 2 j6 ext_clk gnd gnd gnd vcc d1 led d2 led l1 l2 22 h gnd d5 card_a_ins 1 2 j10 crd_vcc_a q2 2n2222 gnd d6 crd_vcc_a 1 2 j9 crd_vcc_b gnd gnd d3 crd_b_ins gnd gnd q1 2n2222 d4 crd_vcc_b a0 a1 a2 a3 card_sel pgm cs pwr_on mux_mode en_rpu status int i/o_a reset_a c4_a c8_a clk_in_a clk_in_b c8_b c4_b reset_b i/o_b e io_a vcc_a rst_a clk_a 1 2 j13 ground 1 2 j14 ground 1 2 j11 ground c1 100 nf c2 100 nf gnd vcc vcc_b c3 10 f 1 tp13 i/o_a 1 tp14 i/o_b status clk_in io_b gnd figure 35. test board schematic diagram 22 h 4.7 f, x7r 4.7 f, x7r 4.7 f, x7r 10 f, x7r gnd
ncn6004a http://onsemi.com 35 figure 36. demo board pcb top overlay
ncn6004a http://onsemi.com 36 figure 37. demo board pcb top layer
ncn6004a http://onsemi.com 37 figure 38. demo board pcb bottom layer note: note: the demo board is built with a four layers pcb, the internal ones being dedicated to v cc and gnd planes.
ncn6004a http://onsemi.com 38 pin functions and description 4 . . . . . . power supply section 10 . . . . . . . . . . . . . . . digital input section @ 2.70 < v cc < 5.50v, normal operating mode 11 . . . . . . . . . . . . . . . . . . card interface section @ 2.70 < v cc < 5.50v, normal operating mode 12 . . . . . . . . . . . . . . . . . . digital dynamic section normal operating mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital dynamic section programming mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming and status functions 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system states upon start up 16 . . . . . . . parallel/multiplexed operation modes 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card power supply timing 18 . . . . . . . . . . . power down operation 18 . . . . . . . . . . . . . . card detection 20 . . . . . . . . . . . . . . . . . . . . . . power management 21 . . . . . . . . . . . . . . . . . . output voltage programming 21 . . . . . . dc/dc converter 22 . . . . . . . . . . . . . . . . . . . . . clock divider 27 . . . . . . . . . . . . . . . . . . . . . . . . parallel operation 30 . . . . . . . . . . . . . . . . . . data i/o level shifter 31 . . . . . . . . . . . . . . . . esd protection 33 . . . . . . . . . . . . . . . . . . . . . . security features 33 . . . . . . . . . . . . . . . . . . . test board schematic diagram 34 . . . . . figures figure 1: pin diagram 2 . . . . . . . . . . . . . . . . . . . . figure 2: typical applications 2 . . . . . . . . . . . . figure 3: block diagram 3 . . . . . . . . . . . . . . . . . figure 4: programming sequence 14 . . . . . . . . figure 5: reading anlg_vcc status 16 . . . . . figure 6: simplified mux_mode logic and multiplex circuit 17 . . . . . . . . . . . . . . . . . . . . . . . . . figure 7: card power supply turn on and shut off typical sequence 18 . . . . . . . . . . . . . . figure 8: card power down sequence 18 . . . . figure 9: power down sequence 19 . . . . . . . . . figure 10: power down sequence: timing details 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11: typical interrupt sequence 20 . . . . . figure 12: card power supply controls 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13: power on sequence timing 22 . . . . figure 14: power on and card_sel sequence timings 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15: basic dc/dc converter diagram 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16: theoretical dc/dc operating 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17: typical crd_vcc ripple voltage 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18: typical card voltage turn on and start?up 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19: typical card supply turn off 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 20: crd_vcc efficiency as a function of the input supply voltage 25 . . . . . . . . . . . . . . . . . . . . figure 21: typical output voltage ripple 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 22: output current limit 26 . . . . . . . . . . . figure 23: output current limit as a function of the temperature 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24: simplified frequency divider and programming functions 27 . . . . . . . . . . . . . . . . . figure 25: clock programming timing s28 . . . figure 26: card clock ? divider operation 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 27: clock divider: 8 to 1 operation 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 28: clock divider timing details 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29: clock divider: run to stop high operation 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29: typical rise and fall time in fast and slow operating mode 30 . . . . . . . . . . . . . . . . . . . . . . . . . figure 30: parallel operation wiring mux_mode = high 30 . . . . . . . . . . . . . . . . . . . . . . figure 31: multiplexed operation wiring mux_mode = low 31 . . . . . . . . . . . . . . . . . . . . . . figure 32: dual bi?directional i/o line level shifter and multiplex 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 33: typical i/o rise and fall time 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 34: test board schematic diagram 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 35: demo board pcb top overlay 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 37: demo board pcb top layer 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 38: demo board pcb bottom layer 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 1 :programming and reading basic functions 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 2: programming functions 15 . . . . . . . . . table 3: status pins data 16 . . . . . . . . . . . . . . . . table 4: operating conditions upon start?up 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 5: card detection polarity 20 . . . . . . . . . . table 6: ceramic/electrolytic capacitors comparison 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 7: programming clock routing 30 . . . . . table 8: output clock slope selection 30 . . . .
ncn6004a http://onsemi.com 39 abbreviations l1a and l1b dc/dc external inductor #a crd_vcc_a interface ic card #a power supply line l2a and l2b dc/dc external inductor #b crd_clk_a interface ic card #a clock in- put cout output capacitor crd_rst_a interface ic card #a reset input crd_vcc card power supply input crd_io_a interface ic card #a data link vcc mpu power supply voltage crd_c4_a interface ic card #a data control icc current at card vcc pin crd_c8_a interface ic card #a data control class a 5 v smart card crd_det_a card insertion/extraction detection cs chip select card_sel card #a/b selection bit crd_clk_b interface ic card #b clock in- put crd_io_b interface ic card #b data link en_rpu enable/disable internal pull up crd_io_b interface ic card #b reset input pgm chip programming mode emv euro card master card visa iso international standards orga- nization class b 3 v smart card crd_vcc_b interface ic card #b power supply line anlg_vcc = vcc = v bat input voltage crd_c4_b interface ic card #b data control pwr_on chip power on bit crd_c8_a interface ic card #b data control mux_mode card multiplex or parallel op. crd_det_b card insertion/extraction detection t0 smart card data transfer pro- cedure by bytes t1 smart card data transfer pro- cedure by strings c microcontroller
ncn6004a http://onsemi.com 40 package dimensions 48 leads, tqfp ep case 932f?01 issue a ??? ??? ??? a1 a t?u m 0.200 z ab 4 pl 48 37 36 1 25 12 13 24 t b1 b u v v1 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums t, u, and z to be determined at datum plane ab. 5. dimensions s and ab to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8. minimum solder plate thickness shall be 0.0076. 9. exact shape of each corner is optional. dim min max millimeters a 7.000 bsc a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 0.900 1.100 d 0.170 0.270 e 0.950 1.250 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 l 0 7 m 12 ref n 0.090 0.160 p 0.250 bsc r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref s s1 z t?u m 0.200 z ac 4 pl detail y ab ac g ad ac 0.080 w c e h aa k l r m top & bot 0.250 gauge plane p ae ae t, u, z detail y n f d j section ae?ae t?u m 0.080 ac z t exposed pad t 5.000 bsc detail ad note 9 seating plane on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncn6004a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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